CMOS circuits are used in a variety of integrated circuit (IC) applications. A CMOS process can be used to fabricate many different sorts of functionality, such as memory, logic, and switching, and thus CMOS techniques are particularly desirable in applications where an IC includes several different types of functional blocks.
One family of ICs employing CMOS fabrication techniques are programmable logic devices (PLDs). PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
ICs are often fabricated on semiconductor wafers, such as a silicon wafer. A semiconductor can generally be P-type, N-type, or intrinsic (where the P-type species essentially equal the N-type species), which refers to the conductivity type of the semiconductor. A common technique used when fabricating CMOS ICs, which have both NMOS field-effect transistors (FETs) and PMOS FETs is to use a semiconductor wafer with a first conductivity type (e.g., a P-type silicon wafer), and then form what are commonly referred to as wells of the second conductivity type (e.g., N-wells). Wells are formed by doping the silicon with atomic species, such as by diffusion or ion implantation, to a higher level than the substrate to achieve the desired conductivity and conductivity type.
One approach to well formation used in conventional IC fabrication is to use thick photoresist to define a well implantation mask, and then implant the desired dopant species to the desired concentration and depth in the well areas. Generally, windows are opened in the thick photoresist where implantation is to occur, and a field implant is performed. Thick photoresist blocks the ions from reaching the substrate.
Unfortunately, ions scatter when impinging the photoresist. If a scattered ion is sufficiently close to the edge of the photoresist (i.e., close to a window in the photoresist), the ion might scatter into the well area. Such scattering can increase the doping level of the well area next to the well edge. Similarly, ions can be deflected off the side of the photoresist into the well area, also increasing the doping level. The increased doping level can in turn cause a significant difference in the threshold voltage of an FET fabricated near the well edge compared to a FET fabricated further from the well edge. This variation in FET performance is known as well proximity effect (WPE).
WPE is a problem in 90 nm node geometry ICs, and becomes increasingly problematic as the critical dimension of the device (commonly referred to as the node technology) decreases. WPE is generally even more of a problem in 65 node geometry ICs, and is expected to have more serious consequences at 20 nm node geometry ICs. Thick photoresist also has lithographic limits that diminish its suitability for small well patterning.
Similarly, as source/drain regions of FETs in an IC become shallower, WPE becomes a more significant contribution to device variation. Device variation is undesirable because many functions of an IC presume that FETs of a particular type are essentially the same and will operate in essentially the same manner. WPE can cause some FETs to operate differently from the rest, which can affect IC operation.
One technique for dealing with WPE is to create sophisticated device models that predict FET operation (e.g., threshold voltage), for different FETs based on where the FET is in relation to the edge of the well. Unfortunately, these models are derived after the IC layout is complete, and while operation of the various FETs is more closely predicted, such techniques do not reduce the distribution of FET performance. In addition to being cumbersome, such techniques add substantial time to the design cycle if the layout of the IC needs to be changed to correct a problem with WPE.
Therefore, techniques for reducing the WPE in small geometry ICs are desirable and useful. It is further desirable and useful to improve well definition in small geometry ICs.